1. Field of the Invention
The present invention relates to a semiconductor device including an NMOS transistor under a pad.
2. Description of the Related Art
A semiconductor device, also called an IC or a semiconductor chip, has a pad as an external connection electrode in order to establish an electrical connection to another element or another semiconductor device. In the vicinity of the pad, an ESD protective circuit is generally provided for protecting an internal circuit of the semiconductor device from electrostatic discharge (ESD). The ESD protective circuit uses a multi-finger NMOS transistor in many cases. In this case, a gate electrode, a source, and a back gate of the NMOS transistor are connected to a ground terminal, and a drain thereof is connected to the pad.
By the way, various approaches are attempted for the ESD protective circuit using the multi-finger NMOS transistor so that respective channels may uniformly operate to increase ESD tolerance of the semiconductor device. Specifically, for example, the technology of Japanese Published Patent Application No. 2011-210904 appropriately controls a distance between a salicide metal film and a gate electrode of the NMOS transistor of the ESD protective circuit. The technology of Japanese Published Patent Application No. 2010-219504 appropriately controls the number of contacts of the source. The technology of Japanese Published Patent Application No. 2007-116049 appropriately controls the channel length. The technologies are each aimed at finely defining the layout of the NMOS transistor.
A surge current caused by ESD is, however, an extremely large and instantaneous current. Consequently it is significantly difficult to define the layout of the NMOS transistor based on the surge current. In contrast, it is practically almost impossible to quantify the dependency of the ESD tolerance on the layout of the NMOS transistor, either.